This invention was developed for use in testing DRAMs, a type of memory integrated circuit, also called a chip. One chip can store thousands of bits. As the chips are manufactured, a method of classifying failures is necessary to improve the production process.
One way to classify a failing memory chip is to count how many "badbits" are in the chip. A good memory chip will faithfully store and retrieve a bit at any location within the chip. A failing memory chip will have one or more locations that do not store or retrieve bits successfully. A faulty location such as this is called a "badbit". Clearly, a memory chip with only one badbit is much closer to functioning than a memory chip with a thousand badbits. Hence, the ability to count badbits is very helpful in identifying failure modes and providing feedback to the production process to minimize those failure modes.
Many commercially available memory testers are able to count badbits, but this can cost extra and can take more test time. The badbit counter described herein is useful as a low-cost addition to any memory tester to add efficient badbit counting ability.
Although the preferred embodiment tests memory circuits, this invention could be used to test any digital device simply by simultaneously comparing the outputs of a known good device with the outputs of a device under test.
Prior art includes a similar technique but a different application, as shown in U.S. Pat. No. 4,752,929/Kantz, et al., which describes methodology and evaluation circuitry for operating a semiconductor memory having test-mode capability. (A chip with test-mode ability can read or write internal multiple bits simultaneously which are normally singly addressed, and provide an output signal indicating when the paralleled bits are not identical, indicating a badbit. The purpose of a test-mode is to reduce testing time, particularly for larger semiconductor memory devices.)
The similarity between the instant claims and those of Kantz, et al., is the comparison of a memory cell under test to a reference memory cell through an XOR gate, and the use of the output signal of the XOR gate to indicate digital discrepancies between said cells.
The differences are:
(1) Kantz, et al., direct their device for use within a particular semiconductor memory device. The instant invention is separate from the device under test, and can be used to test any memory device, as well as other digital devices, or an analog device fed through an analog-to-digital converter. PA1 (2) Kantz, et al., created their invention primarily for test-mode circuitry and methods. The instant invention was created primarily for efficient classification of failures (via badbit counting). The instant invention can be used regardless of the test-mode capability of the device under test.